dm9008aep product brief ethernet controller with general processor interface june 2008 rev.1.0 the dm9008a is a fully integrated and cost-effective low pin count ethernet controller with a general processor interf ace, a medial access control (mac), a 10base-t phy and 16k byte sram. it is designed with low power and high performance process that support 3.3v with 5v io tolerance. the dm9008a supports 8-bit and 16-bit data interfaces to internal memory accesses for various processors. the dm9008a also supports full duplex mode the phy of the dm9008a can in terface to the utp3, 4, 5 in 10base-t that is fully compliant with the ieee 802.3 spec.. the hp auto-mdix function of phy is also supported to improve the medi a connection in convenience. block diagram
specifications 48-pin lqfp supports processor interface: byte/word of i/o command to internal memory data operation comply to 10base-t of ieee 802.3 with hp auto-mdix supports back pressure mode for half-duplex mode flow control support 100m fiber interface. ieee802.3x flow control for full-duplex mode supports wakeup frame, link status change and magic packet events for remote wake up integrated 16k byte sram build in 3.3v to 2.5v regulator supports early transmit supports automatically load vendor id and product id from eeprom optional eeprom configuration very low power consumption mode: C power reduced mode (cable detection) C power down mode C selectable tx drivers for 1:1 or 1.25:1 transformers for additional power reduction. compatible with 3.3v and 5.0v tolerant i/o application voip cpe (ata, ip phone, video phone) ip stb, ipc, internet radio ordering information part number pin count package dm9008aep 48 lqfp (pb-free) davicom semiconductor, inc. no.6, li-hsin rd.vi, science pa rk, hsin-chu, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 e-mail: sales@davicom.com.tw
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